The semiconductor integrated circuit (IC) fabrication process includes front-end-of-line (FEOL) processing for fabricating semiconductor devices, e.g. transistors, and back-end-of-line (BEOL) processing for connecting the individual devices. In particular, the BEOL processing provides interconnects for the devices. The interconnects typically include conductive (e.g., metal) horizontal lines and vertical vias isolated by the dielectric material of the semiconductor device.
Trenches and vertical interconnect accesses (vias) are patterned into the dielectric layer and filled with the conductive material forming wires connecting metal layers and/or devices. As ICs and other semiconductor devices have become smaller, the substructures—including the interconnects—have become smaller, and copper (Cu) has replaced aluminum (Al) as the conductive material. Cu has a lower resistivity and better reliability than Al.
For Cu interconnects, conventional BEOL methods use a damascene process to pattern the trenches and vias into the dielectric material, fill these recesses with interconnect materials, and then planarize the wafer surface. Chemical mechanical polishing (CMP) is used to remove the excess material and planarize the wafer surface. CMP combines a chemical slurry with a mechanical polishing pad to remove the conductive interconnect material in a uniform, planar fashion, providing a smooth, uniform surface, upon which additional dielectric layers and conductive line layers are formed. However, the slurry chemicals are corrosive and degrade the interconnect substructures, leading to reduced reliability for the devices.